1. Field of the Disclosure
The present disclosure relates to processes of forming electronic devices, and more particularly to processes of forming electronic devices including layers formed using inductively coupled plasmas.
2. Description of the Related Art
As device performance becomes more and more demanding, semiconductor devices are now formed using semiconductor-on-insulator (“SOI”) substrates. In order to achieve a reasonably high component density, field isolation regions are typically formed between semiconductor devices. Typically, a liner layer is formed to help round the top corners of a semiconductor layer to improve gate dielectric integrity.
FIG. 1 includes an illustration of a cross-sectional view of a portion of an electronic device. The electronic device includes a substrate 12, an insulating layer 14, which can be a buried oxide, and a semiconductor layer 162 that overlies the insulating layer 14. The semiconductor layer 162 is patterned to form openings that extend through the semiconductor layer 162 to the insulating layer 14. A thermal oxidation is typically performed and grows a liner layer 164. During the formation of the liner layer 164, top corners 166 of the semiconductor layer 162 are rounded in order to improve gate dielectric integrity. However, the thermal oxidation also causes corner rounding near the bottom of the semiconductor layer 162, as seen with rounded bottom corners 168. The rounded bottom corners 168 within the semiconductor layer 162 near the insulating layer 14 are undesired. An insulating layer 18 can then be formed within the openings, with portions of the insulating layer 18 overlying the semiconductor layer 162 being removed using a conventional process. During subsequent thermal cycles, unacceptable levels of stress may be exerted by the field isolation regions (combination of the liner layer 164 and insulating layer 18) onto the semiconductor layer 162. The stress may cause electrical characteristics of the devices to change, defects, faults, fractures to form within the semiconductor layer 162, or, in extreme cases, delamination of the semiconductor layer 162 from the insulating layer 14.
Another attempt to address the bird's beak has been to form the opening extending through the semiconductor layer 162 and form a nitride layer (not illustrated) along the bottom of the opening and not form any of the nitride layer along the sidewalls of the semiconductor layer 162 near the upper corners 166. In theory, the upper corners 166 of the semiconductor layer 162 should be exposed during a subsequent thermal oxidation, while the lower corners 168 are protected. The nitride layer can be deposited by evaporating the nitride layer, sputtering the nitride layer, or using a thermal chemical vapor technique. In practice, this technique does not work.
Sputtering is characterized by a long mean free path and no significant surface migration. Along the sidewalls, the nitride layer will be thicker at the upper corners 166 and thinner at the lower corners 168, when measured in a direction perpendicular to the sidewalls of the semiconductor layer 162. A collimator can reduce the sidewall deposition, but the deposition would still be thicker at the upper corners 166 as compared to the lower corners 168. Thus, thermal oxidation would round the upper corners 166 and the lower corners 168. Evaporation is more conformal and less directional as compared to sputtering. Therefore, a significant amount of the nitride layer will deposit along the sidewall.
A thermal chemical vapor deposition is a deposition performed without using a plasma. When forming a nitride layer using low pressure chemical vapor deposition (“LPCVD”), dichlorosilane and ammonia are typically reacted at a temperature in a range of approximately 700° C. to approximately 800° C. under vacuum and without a plasma. The deposition is characterized by a rapid surface migration and forms a substantially conformal nitride layer, which would deposit about the same thickness of nitride along the bottom of the opening as it would along the sidewalls of the semiconductor layer 162.
Therefore, a layer having a significant thickness along a bottom of an opening no or very little sidewall coverage while protecting the lower corners 168 while allowing rounding the upper corners 166 of the semiconductor layer 162 has not been enabled. Sputtering and evaporating a nitride layer would deposit a layer along the sidewall that would be locally thicker near the upper corners 166 as compared to the lower corners 168, and a thermal CVD process can produce a conformal layer.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.